1. Field of the Invention
The present disclosure generally relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a novel contact landing pad structure for a semiconductor device, and various methods of making such a contact landing pad.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate. The source and drain regions are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Over the years, device features, like the channel length, have been steadily decreased in size to enhance the performance of the transistor, e.g., increase its switching speed, and the overall functionality of the circuit. There is a constant drive in the semiconductor manufacturing industry to decrease the physical size of transistor devices, and thus the “footprint” or “real estate” occupied by a particular circuit, while at the same time increasing device performance capability—i.e., there is a constant drive to increase the packing density on integrated circuit products. However, the ongoing shrinkage of feature sizes on transistor devices and the demand for ever higher packing densities causes the pitch between adjacent transistors to also decrease. In turn, this overall increase in packing density limits the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor or to active regions in the substrate—and makes accurately landing them where desired more challenging as there is less margin for errors due to, for example, misalignment.
FIGS. 1A-1B are, respectively, a plan view and a cross-sectional view of a portion of an integrated circuit device, that are provided to explain one prior art technique that is employed to form contacts to active regions formed in a semiconducting substrate. Such contacts may be formed for a variety of purposes, e.g., to provide electrical contact to a doped well region formed in an active region. As shown therein, a plurality of isolation structures 12 are formed in the substrate 10 to thereby define active regions 10A, 10B. The isolation structures 12 may be formed by etching trenches into the substrate 10 and thereafter filling the trenches with an insulating material, such as silicon dioxide. Typically, in current-generation devices, the depth 12D of the isolation regions is about 250 nm so as to insure good electrical isolation between adjacent active regions. To insure that the trench can be reliably filled without formation of undesirable voids, the width 12W of the trench where the isolation region 12 will be formed has a minimum size of about 60 nm, i.e., the aspect ratio of the trench is a little greater than 4 (250/60).
Illustrative contacts 14 are depicted on the region 10B. The contacts 14 may take any form or shape, such as the illustrative square post configuration depicted in the drawing or it may take the form of a line-type structure. In general, the width 10W of the active regions 10A, 10B must be large enough to tolerate any potential misalignment between the contact 14 and the active region. What is undesirable is for any portion of the contact 14 to land outside of the active region, i.e., on the isolation region 12. If that situation were to occur, portions of the isolation structure 12 might be consumed in the process of forming the contacts 14, thereby reducing the effectiveness of the isolation region 12 and perhaps leading to the formation of conductive material in undesirable locations that, in a worst case scenario, might lead to device failure.
By way of example, if the contacts 14 have a width 14W of 30 nm, then the active regions 10A, 10B may be formed to a width 10W of about 50 nm so as to accommodate some misalignment between the contact 14 and the active region 10B. Unfortunately, making the active regions 10A, 10B wider so as to insure that the contacts 14 do not land outside of the active regions 10A, 10B increases the pitch 10P between the active regions 10A, 10B. In the example just discussed, the pitch 10P would be 110 nm (50 nm active width+60 nm trench width). This increased pitch 10P means that valuable plot space or “real estate” is consumed for the purpose of forming contacts 14 to active regions 10A, 10B.
The present disclosure is directed to towards a novel contact landing pad structure for a semiconductor device, and various methods of making such a contact landing pad, that may avoid, or at least reduce, the effects of one or more of the problems identified above.